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1. features ? one of a family of devices with user memories from 1-kbit to 8-kbits ? 2-kbit (256-byte) eeprom user memory ? four 512-bit (64-byte) zones ? self-timed write cycle ? single byte or 16-byte page write mode ? programmable access rights for each zone ? 2-kbit configuration zone ? 37-byte otp area for user-defined codes ? 160-byte area for user-defined keys and passwords ? high security features ? 64-bit mutual authentication prot ocol (under license of elva) ? cryptographic message authentication codes (mac) ? stream encryption ? four key sets for authen tication an d encryption ? eight sets of two 24-bit passwords ? anti-tearing function ? voltage and frequency monitors ? smart card features ? iso 7816 class b (3v) operation ? iso 7816-3 asynchronous t=0 protocol (gemplus? patent) ? multiple zones, key sets and passwords for multi-application use ? synchronous 2-wire serial interf ace for faster device initialization ? programmable 8-byte answer-to-reset register ? iso 7816-2 compliant modules ? embedded application features ? low voltage supply: 2.7v ? 3.6v ? secure nonvolatile storage for sensitive system or user information ? 2-wire serial interface (twi, 5v compatible) ? 1.0 mhz compatibility for fast operation ? standard 8-lead plastic packages, green compliant (exceeds rohs) ? same pin configuration as at24cxxx serial eeprom in soic and pdip packages ? high reliability ? endurance: 100,000 cycles ? data retention: 10 years ? esd protection: 2,000v min table 1-1. pads pad description iso module ?soic, pdip? tssop mini- map vcc supply voltage c1 8 8 4 gnd ground c5 4 1 5 scl/clk serial clock input c3 6 6 2 sda/io serial data input/output c7 5 3 7 rst reset input c2 nc nc nc cryptomemory ? at88sc0204ca summary 5202cs?crypt?5/09
2 5202cs?crypt?5/09 at88sc0204ca 2. description the at88sc0204ca member of the cryptomemory? family is a high-performance secure memory providing 2 kbit of user memory with ad vanced security and cryptographic features built in. the user memory is divided into four 64-byt e zones, each of which may be individually set with different security access ri ghts or effectively combined toget her to provide space for 1 to 4 data files. the at88sc0204ca features an en hanced command set that allows direct communi- cation with microcontroller hardware 2-wire in terface thereby allowing for faster firmware development with reduced code space requirements. 3. smart card applications the at88sc0204ca provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. t he embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. up to four unique key sets may be used for these o perations. the at88sc0204c a offers the ability to communicate with virtually any smart card reader using the asynchronous t = 0 protocol (gem- plus patent) defined in iso 7816-3. 4. embedded applications through dynamic, symmetric-mutual authentication, data encryption, and the use of crypto- graphic message authentication codes (mac), th e at88sc0204ca provides a secure place for storage of sensitive information wi thin a system. with its tamper detection circuits, this informa- tion remains safe even under attack. a 2-wire serial interface running at speeds up to 1.0 mhz provides fast and efficient communications with up to 15 individually addressable devices. the at88sc0204ca is available in industry standard 8- lead packages with the same familiar pin configuration as at24c xxx serial eeprom devices. note: does not apply to tssop pinout. 1 2 3 4 8 7 6 5 smart card module vcc=c1 rst=c2 scl/clk=c3 nc=c4 c5=gnd c6=nc c7=sda/io c8=nc 8-lead soic, pdip nc nc nc gnd vcc nc scl sda 8-lead tssop nc 1 8 vcc nc 27nc 8-lead tssop nc 3 6 clk gnd 45 sda 1 2 3 4 8 7 6 5 sda gnd clk vcc 8-lead ultra thin mini-map (mlp 2x3) bottom view nc nc nc nc
3 5202cs?crypt?5/09 at88sc0204ca figure 4-1. block diagram 5. connection diagram figure 5-1. connection diagram random generator authentication, encryption and certification unit eeprom answer to reset data transfer password verification reset block asynchronous iso interface synchronous interface power management vcc gnd scl/clk sda/io rst 2.7v - 5.5v 2.7v - 3.6v sda scl microprocessor cryptomemory
4 5202cs?crypt?5/09 at88sc0204ca 6. pin descriptions 6.1 supply voltage (vcc) the vcc input is a 2.7v to 3.6v pos itive voltage supplied by the host. 6.2 clock (scl/clk) when using the asynchronous t = 0 protocol, t he clk (scl) input provi des the device with a carrier frequency f. the nominal length of one bit emitted on i/o is defined as an ?elementary time unit? (etu) and is equal to 372/f. when using the synchronous protoc ol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the clock when reading from the device. 6.3 reset (rst) the at88sc0204ca provides an iso 7816-3 compliant asynchronous answer-to-reset (atr) sequence. upon activation of t he reset sequence, the device outputs bytes contained in the 64- bit answer-to-reset register. an internal pull-up on the rst input pad allows the device to oper- ate in synchronous mode without bonding rst. the at88sc0204ca does not support an answer-to-reset sequence in the synchronous mode of operation. 6.4 serial data (sda/io) the sda/io pin is bidirectional for serial data tr ansfer. this pin is open-drain driven and may be wired with any number of other open-drain or open- collector devices. an ex ternal pull-up resistor should be connected between sda/io and vcc. t he value of this resistor and the system capacitance loading the sda/ io bus will determine the rise time of sda/io. this rise time will determine the maximum fr equency during read operations. low value pu ll-up resistors will allow higher frequency operations while drawing higher average power supply current. sda/io infor- mation applies to both asynchro nous and synchronous protocols.
5 5202cs?crypt?5/09 at88sc0204ca 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions bey ond those indicated in the oper- ational sections of this specification is not implied. exposure to ab solute maximum rating conditions for extended periods of time may affect device reliability. absolute maximum ratings operating temperature ..................................... -40 ? c to +85 ? c storage temperature ..........................................? 65 ? c to +150 ? c voltage on any pin with respect to ground .................................... ? 0.7 to v cc +0.7v maximum operating voltage............................................. 6.0v dc output current ........................................................ 5.0 ma table 7-1. dc characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c (unless otherwise noted) symbol parameter test co ndition min typ max units v cc (1) supply voltage 2.7 3.6 v i cc supply current async read at 3.57mhz 5 ma i cc supply current async write at 3.57mhz 5 ma i cc supply current synch read at 1mhz 5 ma i cc supply current synch write at 1mhz 5 ma i sb standby current vin = vcc or gnd 100 ua v il sda/io input low voltage 0 vcc x 0.2 v v il clk input low voltage 0 vcc x 0.2 v v il rst input low voltage 0 vcc x 0.2 v v ih (1) sda/io input high voltage vcc x 0.7 5.5 v v ih (1) scl/clk input high voltage vcc x 0.7 5.5 v v ih (1) rst input high voltage vcc x 0.7 5.5 v i il sda/io input low current 0 < vil < vcc x 0.15 15 ua i il scl/clk input low current 0 < vil < vcc x 0.15 15 ua i il rst input low current 0 < vil < vcc x 0.15 50 ua i ih sda/io input high current vcc x 0.7 < vih < vcc 20 ua i ih scl/clk input high current vcc x 0.7 < vih < vcc 100 ua i ih rst input high current vcc x 0.7 < vih < vcc 150 ua v oh sda/io output high voltage 20k ohm external pull-up vcc x 0.7 vcc v v ol sda/io output low volt age iol = 1ma 0 vcc x 0.15 v
6 5202cs?crypt?5/09 at88sc0204ca i oh sda/io output high current voh 20 ua i ol sda/io output low current vol 10 ma note: 1. to prevent latch up conditions from occurring during power up of the at88sc0204ca, v cc must be turned on before applying v ih . for powering down, v ih must be removed before turning v cc off. table 7-2. ac characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c, cl = 30pf (unless otherwise noted) parameter min max units f clk async clock frequency 1 4 mhz f clk synch clock frequency 0 1 mhz clock duty cycle 40 60 % t r ?rise time - sda/io, rst? 1 us t f ?fall time - sda/io, rst? 1 us t r rise time - scl/clk 9% x period us t f fall time - scl/clk 9% x period us t aa clock low to data out valid 250 ns t hd.sta start hold time 200 ns t su.sta start set-up time 200 ns t hd.dat data in hold time 10 ns t su.dat data in set-up time 100 ns t su.sto stop set-up time 200 ns t dh data out hold time 20 ns t wr write cycle time 5ms table 7-1. dc characteristics (continued) applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c (unless otherwise noted) symbol parameter test co ndition min typ max units
7 5202cs?crypt?5/09 at88sc0204ca 8. device operations for synchronous protocols 8.1 clock and data transitions the sda pin is normally pulled high with an exte rnal device. data on the sda pin may change only during scl low time periods (see figure 8-3 on page 8 ). data changes during scl high periods will indicate a start or st op condition as defined below. 8.1.1 start condition a high-to-low transition of sda with scl high defines a start condition which must precede all commands (see figure 8-4 on page 8 ). 8.1.2 stop condition a low-to-high transition of sda with scl high de fines a stop condition. after a read sequence, the stop condition will place the ee prom in a standby power mode (see figure 8-4 on page 8 ). 8.1.3 acknowledge all addresses and data words ar e serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has received each word. this happens dur- ing the ninth clock cycle (see figure 8-5 on page 9 ). 8.2 memory reset after an interruption in communication due protocol errors, power loss or any reason, perform "acknowledge polling" to properly recover from the condition. acknow ledge polling consists of sending a start condition followed by a vali d cryptomemory command byte and determining if the device responded with an acknowledge. figure 8-1. bus time for 2-wire serial communications. scl: serial clock, sda: serial data i/o
8 5202cs?crypt?5/09 at88sc0204ca figure 8-2. write cycle timing. scl: serial clock, sda: serial data i/o note: the write cycle time twr is the time from a va lid stop condition of a writ e sequence to the end of the internal clear/write cycle. figure 8-3. data validity figure 8-4. start and stop definitions t wr (1) stop condition start condition wordn ack 8th bit s cl s da data change allowed
9 5202cs?crypt?5/09 at88sc0204ca figure 8-5. output acknowledge
10 5202cs?crypt?5/09 at88sc0204ca 9. device architecture 9.1 user zones the eeprom user memory is divi ded into 4 zones of 512 bits each. multiple zones allow for storage of different types of data or files in different zones. access to user zones is permitted only after meeting proper security requirements . these security requirements are user definable in the configuration memory during device personalization. if the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. table 9-1. user zone zone $0 $1 $2 $3 $4 $5 $6 $7 user 0 $00 - 64 bytes - $38 user 1 $00 - 64 bytes - $38 user 2 $00 - 64 bytes - $38 user 3 $00 - 64 bytes - $38
11 5202cs?crypt?5/09 at88sc0204ca 10. control logic access to the user zones occur only through the c ontrol logic built into the device. this logic is configurable through access registers, key regi sters and keys programmed into the configuration memory during device personalization. also impl emented in the control logic is a cryptographic engine for performing the various higher-l evel security functions of the device. 11. configuration memory the configuration me mory consists of 2048 bits of eeprom memory used for storage of pass- words, keys, codes, and also used for definition of security access rights for the user zones. access rights to the configurat ion memory are defined in the control logic and are not alterable by the user after comple tion of personalization. figure 11-1. configuration memory $0 $1 $2 $3 $4 $5 $6 $7 $00 answer to reset identification $08 fab code mtz card manufacturer code $10 lot history code read only $18 dcr identification number nc access control $20 ar0 pr0 ar1 pr1 ar2 pr2 ar3 pr3 $28 reserved $30 $38 $40 issuer code $48 $50 for authentication and encryption use cryptography $58 $60 $68 $70 $78 $80 $88 $90 for authentication and encryption use secret $98 $a0 $a8 $b0 pac write 0 pac read 0 password $b8 pac write 1 pac read 1 $c0 pac write 2 pac read 2 $c8 pac write 3 pac read 3 $d0 pac write 4 pac read 4 $d8 pac write 5 pac read 5 $e0 pac write 6 pac read 6 $e8 pac write 7 pac read 7 $f0 reserved forbidden $f8
12 5202cs?crypt?5/09 at88sc0204ca 11.1 security fuses there are three fuses on the device that must be blown during the device personalization pro- cess. each fuse locks certain portions of the configuration zone as otp (one-time programmable) memory. fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequenc e, although all programming of the device and blowing of the fuses may be performed at one final step. 12. communication security modes communications between the device and host operate in three basic modes. standard mode is the default mode for the device after power-up. authentication mode is activated by a successful authentication sequence. encryption mode is ac tivated by a successful encryption activation fol- lowing a successful authentication. note: 1. configuration data include viewable areas of the configuration zone except the passwords: mdc: modification detection code. mac: message authentication code. 13. security options 13.1 anti-tearing in the event of a power loss during a write cycle, t he integrity of the device?s stored data is recov- erable. this function is optional: the host may choose to activate the anti-tearing function, depending on application requirements. when anti -tearing is active, write commands take longer to execute, since more write cycl es are required to complete them, and data is limited to a maxi- mum of eight bytes for each write request. data is written first into a buffer zone in eeprom instead of the intended destination address, but with the same access conditions. the data is then written in the required location. if this sec- ond write cycle is interrupted due to a power lo ss, the device will automa tically recover the data from the system buffer zone at the next power-up. non-volatile buffering of the data is done automatically by the device. during power-up in applications using anti-tear ing, the host is required to perform ack polling in the event that the devi ce needs to carry out the data recovery process. table 12-1. communication security modes (1) mode configuration data user data passwords data integrity check standard clear clear clear mdc (1) authentication clear clear encrypted mac (1) encryption clear encrypted encrypted mac (1)
13 5202cs?crypt?5/09 at88sc0204ca 13.2 write lock if a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. for example, the write lock byte at $080 controls the bytes from $081 to $087. figure 13-1. write lock example the write-lock byte itself may be locked by wr iting its least significant (rightmost) bit to ?0?. moreover, when write lock mode is activated, the write lock byte can only be programmed ? that is, bits written to ?0? cannot return to ?1?. in the write lock configuration, write operations are limited to writing only one byte at a time. attempts to write more th an one byte will result in writing of just the first byte into the device. 13.3 password verification passwords may be used to protect read and/or write access of any user zone. when a valid password is presented, it is memorized and active until power is turned off, unless a new pass- word is presented or rst becomes active. there are eight password sets that may be used to protect any user zone. only one password is active at a time. presenting the correct write password also grants read access privileges. 13.4 authentication protocol the access to a user zone may be protected by an authentication protocol. any one of four keys may be selected to use with a user zone. authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or rst becomes active. if the new aut hentication request is not vali- dated, the card loses its previous authentication which must be presented again to gain access. only the latest request is memorized. address $0 $1 $2 $3 $4 $5 $6 $7 $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked
14 5202cs?crypt?5/09 at88sc0204ca figure 13-2. password and authentication operations note: authentication and password verification may be attempted at any time and in any order. exceeding corresponding authentic a- tion or password attempts trial limit renders subsequent authentication or password verification attempts futile. 13.5 cryptographic messag e authentication codes at88sc0204ca implements a data validity che ck function in the standard, authentication or encryption modes of operation. in the standard mode, data validity check is done through a modification detection code (mdc), in which the host may read an mdc from the devic e in order to verify that the data sent was received correctly. in authentication and encryption modes, the data validity check becomes more powerful since it provides a bidirectional data inte grity check and data or igin authentication capability in the form of a message authentication codes (mac). only the host/device that carried out a valid authen- tication is capable of computing a valid mac. while operating in the authentication or encryption modes, the use of mac is required. for an ingoin g command, if the device calculates a mac dif- ferent from the mac transmitted by the host, not only is the command abandoned but the security privilege is revoked. a new authenticatio n and/or encryption activation will be required to reactivate the mac. cs verify cs write data verify rpw data checksum (cs) verify cs
15 5202cs?crypt?5/09 at88sc0204ca 13.6 encryption the data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. the issuer may choose to require encryption for a user zone by settings made in the configura- tion memory. any one of four keys may be select ed for use with a user zone. in this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. even if not required, the host may still elect to activate encryption provided the proper keys are known. 13.7 supervisor mode enabling this feature allows the holder of one s pecific password to gain fu ll access to all eight password sets, including the ability to change passwords. 13.8 modify forbidden no write access is allowed in a user zone protec ted with this feature at any time. the user zone must be written during device personalization prior to blowing the security fuses. 13.9 program only for a user zones protected by this feature, dat a can only be programmed (bits change from a ?1? to a ?0?), but not erased (bits change from a ?0? to a ?1?). 14. protocol selection the at88sc0204ca supports two di fferent communication protocols. smartcard applications: smartcard applications use iso 7816-b protocol in asynchronous t = 0 mode for compatibility and interoperability with indust ry standard smar tcard readers. embedded applications: a 2-wire serial interface provides fast and effici ent connectivity with othe r logic devices or micro- controllers. the power-up sequence determines establishes t he communication protocol for use within that power cycle. protocol selection is allowed only during power-up. 14.1 synchronous 2-wire serial interface the synchronous mode is the default mode after power up. this is due to the presence of an internal pull-up on rst. for embedded applicatio ns using cryptomemory in standard plastic packages, this is the only available communication protocol. power-up vcc, rst goes high also. after stable vcc, scl(clk) and sda(i/o) may be driven.
16 5202cs?crypt?5/09 at88sc0204ca once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device. figure 14-1. synchronous 2-wire protocol note: five clock pulses must be sent before the first command is issued. 14.2 asynchronous t = 0 protocol this power-up sequence complies to iso 7816-3 for a cold reset in sm art card applications. vcc goes high; rst, i/o (sda) and clk (scl) are low. set i/o (sda) in receive mode. provide a clock signal to clk (scl). rst goes high after 400 clock cycles. the device will respond with a 64 -bit atr code, including historic al bytes to indicate the memory density within the cr yptomemory family. once asynchronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. figure 14-2. asynchronous t = 0 protocol (gemplus patent) 15. initial device programming enabling the security features of cryptomemory requires prior personalization. personalization entails setting up of desired access rights by zones, passwords and key values, programming these values into the configuration memory with verification using simple write and read commands, and then blowing fuses to lock this information in place. gaining access to the configuration memory requ ires successful present ation of a secure (or transport) code. the initial signature of the secure (transport) code for the at88sc0204ca v cc i/o-sda rst clk-scl 1 2 3 45 v cc i/o-sda rst clk-scl at r
17 5202cs?crypt?5/09 at88sc0204ca device is $e5 47 47. this is the same as the write 7 password. the user may elect to change the signature of the secure code anyt ime after successful presentation. after writing and verifying data in the configurat ion memory, the security fuses must be blown to lock this informatio n in the device. for additional information on personalizing cryptomemory, please see the application notes programming cryptomemory for embedded applications and initializing cryptomemory for smart card applications from the product page at www.atmel.com/products/securemem. 16. ordering information note: 1. formal drawings may be obtained from an atmel sales office. ordering code package voltage range temperature range at88sc0204ca-mj at88sc0204ca-mp m2 ? j module m2 ? p module 2.7v?3.6v commercial (0c to 70c) at88sc0204ca-pu at88sc0204ca-su at88sc0204ca-tu 8p3 8s1 8a2 2.7v?3.6v green compliant (exce eds rohs)/industrial ( ? 40c to 85c) at88sc0204ca-wi 7 mil wafer 2.7v?3.6v industrial ( ? 40c to 85c) package type (1) description m2 ? j module m2 iso 7816 smart card module m2 ? p module m2 iso 7816 smart card module with atmel ? logo 8p3 8-lead, 0.300? wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150? wide, plastic gull wing small outline pack age (jedec soic) 8a2 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop)
18 5202cs?crypt?5/09 at88sc0204ca 17. packaging information note: the module dimensions listed refer to the dimensions of the exposed metal contact area. the actual dim ensions of the modul e after excise or punching from the carrier tape are generally 0. 4 mm greater in both directions (i.e., a punched m2 module will yield 13.0 x 11.8 mm). module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: square - 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ordering code: mp module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: round - 8.5 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ? ordering code: mj *note: the module dimensions listed refer to the dimensions of the exposed metal contact area. the actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched m2 module will yield 13.0 x 11.8 mm).
19 5202cs?crypt?5/09 at88sc0204ca 18. ordering code: su 18.1 8-lead soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? 8 ? ? e e 1 1 n n top view t o p v i e w c c e1 e 1 end view a a b b l l a1 a 1 e e d d side view s i d e v i e w
20 5202cs?crypt?5/09 at88sc0204ca 19. ordering code: pu 19.1 8-lead pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
21 5202cs?crypt?5/09 at88sc0204ca 19.2 8-lead tssop
22 5202cs?crypt?5/09 at88sc0204ca 20. revision history table 20-1. revision history doc. rev. date comments 5202cs 5/2009 added mini-map column to table 1-1 and mini-map pin-out drawing 5202bs 2/2009 connection diagram inserted; dc characteristics table updated. 5202as 7/2008 initial document release.
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